A block diagram is given below: Block A contains only two flip-flops. Block B contains a one-bit…
A block diagram is given below:
Block A contains only two flip-flops. Block B contains a one-bit adder with SUM and COUT outputs connected to two flip-flops as shown below.
(a) Using the logic gates with propagation delays listed below, determine the setup time for A, B, and CIN with respect to clkshift.
(b) Assuming T = 0 ns and TCLK (clock period) = 5 ns, if data at A, B and CIN become valid and stable 4 ns after the positive edge of clkshift, will there be any timing violations? Assume tH (hold time) = 3 ns for the flip-flop.
(c) How can you eliminate the timing violations? Show your calculations and draw a timing diagram with no timing violations.